This invention relates in general to digital computer systems, and in particular to the ability of a device on a system bus to independently adjust the timing of the interrupt acknowledge cycle.
A computer system usually has a Central Processing Unit (CPU) communicating with a host of peripheral devices through a system bus. To provide interrupt service, the CPU is typically provided with at least a pair of terminals for receiving an interrupt request and for transmitting an interrupt acknowledge.
Any one of the peripheral devices, at any time during its operation may require the attention of the CPU. In particular, one or more interrupt sources within the peripheral could have the peripheral initiate an interrupt cycle by asserting an interrupt request to the CPU. For example, if the peripheral serves as a serial port, one interrupt source could be the Data Carrier Detect (DCD) and another interrupt source could be from the baud rate generator.
When the CPU receives an interrupt request, its first task is to obtain information about which interrupt source made the request and the corresponding address of the appropriate interrupt service to perform. The information is contained in an interrupt vector put out by the peripheral and is fetched by the CPU during an interrupt acknowledge cycle.
After an interrupt request is received, the CPU begins the cycle by issuing an interrupt acknowledge to the peripheral in question. The peripheral, on receiving the acknowledge, determines which of its interrupt sources has made the interrupt request and puts out this information, among other things, in the form of an interrupt vector on the data bus. In the meantime, the CPU issues a read strobe to latch the interrupt vector from the bus and completes the interrupt acknowledge cycle. The length of the interrupt acknowledge cycle is the time interval between the issuance of the interrupt acknowledge and the reading of the interrupt vector. It is generally predetermined for a given CPU.
On the other hand, the peripheral takes a certain amount of time from the reception of the interrupt acknowledge to get the interrupt vector ready on the data bus. Thus, it is essential that the reading is done after the interrupt vector is valid on the data bus. In other words, the timing specification is such that the length of the interrupt acknowledge cycle must be longer than the vector ready time.
The vector ready time is inherently different for different peripheral devices. This is primarily due to the finite time required for signals to settle in the internal device logic which is used to prioritize the different interrupt sources. For example, daisy chain is a common topology employed in prioritizing circuits, and the propagation delays is dependent on the number of links in the chain which in turn is dependent on the number of interrupt sources.
There are two ways of lengthening the interrupt acknowledge cycle so that the timing specification is satisfied. The first way is to program a number of software wait states to delay the read strobe. This has the disadvantage of introducing another possible source of system design error. In any case, most CPU's support only a limited number of software wait states and the method is not applicable to situations where a long delay is required. The second method is to add the wait state by hardware control. A "watchdog" external logic senses the interrupt acknowledge signal and asserts the WAIT input of the CPU for a predetermined time interval so that a number of wait states are inserted. This method has the disadvantage of requiring additional external logic. Another disadvantage is that the timing of the external logic is derived from the system clock, and a change of the system clock necessitates adjusting the timing of the external logic.
In conventional systems, when a number of peripheral devices with differing vector ready times coexist in the same system, the length of the interrupt acknowledge cycle must be determined by the slowest device. In this way, even the worst case situation is also covered. However, this summary approach necessarily puts a penalty on the rest of the peripherals which do not require as long a cycle time. Another disadvantage is that every time a new peripheral is added to the system, its vector ready time must be considered, and if it is slower than all the existing ones, the interrupt acknowledge cycle must be further lengthened to be commensurate with it.
Accordingly, it is a primary object of the invention to allow a peripheral device to indepedently adjust the timing of the interrupt acknowledge cycle.
It is another object of the invention to customize the timing of the interrupt acknowledge cycle to each peripheral.
It is another object of the invention to derive the timing of the interrupt acknowledge cycle by an independent timing circuit within the peripheral device so that the timing is not affected by any change in any external clocks.